The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing FinFET devices that have unmerged source/drain structures.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
The ever shrinking dimensions in future technologies requires tall (on the order of 50 nm or greater) semiconductor fins to meet current density per unit footprint requirements. At the same time, semiconductor fin pitch is also shrinking. Unmerged source/drain epitaxy has emerged as a front-up option compared to merged source/drain epitaxy.
Growing single step unmerged epitaxy source/drain structures on tall semiconductor fins with a tight pitch (on the order of 35 nm or less) cannot work due to geometric reasons, which will lead unavoidably to merged source/drain structures. One approach to formed unmerged source/drain structure by epitaxy includes covering a bottom portion of the semiconductor fins with a spacer and thereafter growing the source/drain structures by epitaxy on the upper portion of the semiconductor fins. Such a technique however leads to non-uniform dopant distribution since the dopant is present only at the top of the tall semiconductor fins.
In view of the above, there is a need for providing a method that can form epitaxial source/drain structures that avoid the drawbacks mentioned with prior art processes.